The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing. For these advances to be realized, similar developments in IC processing and manufacturing are needed. For example, the need to perform higher resolution lithography processes grows. One lithography technique is extreme ultraviolet lithography (EUVL). Other techniques include X-Ray lithography, ion beam projection lithography, electron beam projection lithography, and multiple electron beam maskless lithography.
The EUVL employs scanners using light in the extreme ultraviolet (EUV) region, having a wavelength of about 1-100 nm. Some EUV scanners provide 4X reduction projection printing, similar to some optical scanners, except that the EUV scanners use reflective rather than refractive optics, i.e., mirrors instead of lenses. EUV scanners provide the desired pattern on an absorption layer (“EUV” mask absorber) formed on a reflective mask. Currently, binary intensity masks (BIM) are employed in EUVL for fabricating integrated circuits. EUVL is very similar to optical lithography in that it needs a mask to print wafers, except that it employs light in the EUV region, i.e., at 13.5 nm. At the wavelength of 13.5 nm or so, all materials are highly absorbing. Thus, reflective optics rather than refractive optics is used. A multi-layered (ML) structure is used as a EUVL mask blank. However, any microscopic nonflatness on the substrate will deform the films deposited subsequently. A small bump or pit will introduce a defect. The detrimental effect of a mask defect includes magnified errors to a plurality of wafers.
Therefore, what is needed is the method for a lithography process and a lithography system to address the above issues.